;**************************************************************************
;
;  SWPC.MAC   This is revised for 04-Oct-1991 Experiment. 
;		(Plastic 1 --> 2 )
;  SWPC,MAC   This is a Program for 26-Jul-1990 Experimet.
;
;  Data format
;
;  RID=1
;
;  1   4208 RTDC 0   1-Drift
;  2   4208 RTDC 1   2-Drift
;  3   AD 811 ch 0   1-Low
;  4   AD 811 ch 1   1-High
;  5   AD 811 ch 2   2-Low
;  6   AD 811 ch 3   2-High
;  7   AD 811 ch 4   1 DE
;  8   AD 811 ch 5   2-DE
;  9   QDC-0    Plastic 1 L
; 10   QDC-1    Plastic 1 H
; 11   TDC-0   (RF TOF 1)
; 12   TDC-1   (RF TOF 2)
; 13   QDC-0	Plastic 2 L
; 14   QDC-2    Plastic 2 H
;
;
;						90/05/09   Takashi Ichihara
;  This is an example of Starburst code of RIKEN  Ring Cyclotron Data 
;  acquisition system of multi-crate version. 
;						 90/04/27  Takashi Ichihara
;
;**************************************************************************
;    Among many crates, there should be one master crate (crate Address = 0)
;  which will generate interrupt signal to the host (Micro VAX) computer 
;  requesting the DMA data transfer.  The other crates (slave crate)  will 
;  not generate interrupt to the host.
;
; Some special input
;
;    EXT INT 1: is used for the triggar of each event. This shuld be TTL 
;  	        negative-logic.(usually +5 V.  +0V means interupt signal)
;	        isrev1:: is called by this signal.
;
;    EXT INT 2: is used to change buffer. If the buffer of one of the crate
;               is filled, then the Starburst of the crate will output a
;	        buffer-full signal via output resister bit XX.
;	        The logical OR of the buffer-fill of each crate should be
;	        connected to this EXT INT 2 of each crate:    
;	        isrev2:: is called by this signal.
;
; Some special output
;
;   Output Resister bit 10  (of 1-16)  ---   Ready for next event
;
;   Output Resister bit 15 (of 1-16)  ---    Buffer is full.
;
;
;=========================================================================
;  Multi-carate mode parameters
;=========================================================================

	BUFL=36000	; buffer length of this crate in byte (8 KB = 20000)
			; total buffer length of all crate should be
			; 16 KB or less. The first 8-byte of the buffer
			; is reserved for buffer header and cannot be used
			; for data.

	CADDR=0		; This is a crate address starting from zero.
			; CADDR=0 is master crate. this address is writen
			; in the buffer header.

        NEXTCR=0        ; =1 if the next crate exsists.
			; =0 if this is the last crate.

        MAXEVL=400      ; possible max event length in byte for one event.
;
;=========================================================================
;
;
;  CAMAC Module Station number definition
;
        NSCA=1.			; Scaler
	NCR1=3.			; Coincidence Regisiter 1
	NOPR=6.			; Output Register
	NODC1=7.		; ORTEC ADC 
	NQDC1=9.		; Lectoy ADC
        NRTDC=11.               ; 4208 TDC
	NTDC1=12.		; TDC-1 (Beam Counter)
	NIR1= 19.		; Input Register

	HEAD=167000		; Event Header (EE(H))

	NC  =  30.		; data way c
	NZ  =  31.		; data way z
	
	A0=0			; subaddress of ADC ch 1
	A1=1			; subaddress of ADC ch 2
	A2=2			; subaddress of ADC ch 3
	A3=3			; subaddress of ADC ch 4
	A4=4			; subaddress of ADC ch 5
	A5=5			; subaddress of ADC ch 6
	A6=6			; subaddress of ADC ch 7
	A7=7			; subaddress of ADC ch 8

;
;  Some constant definition
;
	A=2			; CAMAC subaddress offset
	N=32.			; CAMAC station number offset
	ACCBS=164000		; Base address for CAMAC io
	ACCFN=166000		; Function resister
	ACCDH=166002		; Data high and status reg.
	ACCIM=166004		; Interrupt enable reg.
	mask= 170000		; Dama mask bit
        BUFEND=177777		; end of buffer
	BUFFUL=100000		; buffer is full (bit 16 of opr)
;
;  Interupt vector, enable bit, clear bit, and priorities,
;
	VECOVR=374		; CAMAC overrun
	VECLAM=364		; CAMAC LAM
	VECSWI=360		; Software interupt (from Host processor)
	VECIN2=354		; External int 2
	VECIN1=350		; External int 1
	VECQXE=344		; Q/X error
	VECCTO=340		; CAMAC time out

	ICBOVR=  1		; CAMAC overrun
	ICBLAM=  4		; CAMAC LAM
	ICBSWI= 10		; Software interupt (from Host processor)
	ICBIN2= 20		; External int 2
	ICBIN1= 40		; External int 1
	ICBQXE=100		; Q/X error
	ICBCTO=200		; CAMAC time out

	IEBOVR=  1*400		; CAMAC overrun
	IEBLAM=  4*400		; CAMAC LAM
	IEBSWI= 10*400		; Software interupt (from Host processor)
	IEBIN2= 20*400		; External int 2
	IEBIN1= 40*400		; External int 1
	IEBQXE=100*400		; Q/X error
	IEBCTO=200*400		; CAMAC time out
	ENDISR=  2*400		; end of isr1

	PRIO4 = 200		; Interupt priority 4
	PRIO5 = 240		; Interupt priority 5
	PRIO6 = 300		; Interupt priority 6
	PRIO7 = 340		; Interupt priority 7
				;
				;  Data TAG word
				;

;**************************************************************************
;   Some MACRO definitions for CAMAC operation
;**************************************************************************
; WAITQ  : Wait Q becomes 1 (for checking the conversion end of ADC etc.)
; BREAD  : Address scan block read ( read continious channel of ADC etc.)
; F      ; set F code
; F0     : set F=0
; NAF    : execute single camac control operation
; NAR    : execute single camac read    operation
; NAW    : execute single camac write   operation
;
;
;**************************************************************************

	; WAITQ
	;
	; This is a macro for waiting Q set 
	; (waiting for conversion end of the ADC or TDC)
	;
	; nn	= station number of the module
	; aa	= sub address for check the Q responce
	; ff	= function code for check the Q responce
	; maxl  = number of loop waiting for Q asserts
	; qstil0= statement label to jump if Q=0 after maxl trial
	;
	; register to be distroyed (r4)
	;
	.macro	waitq,nn,aa,ff,maxl,qstil0,?L1,?L2
	mov	#maxl,r4			;* R4 loop count
	mov	#ff,@#accfn		;* set F code
L1:	tst	@#<accbs+<nn*n>+<aa*a>> ;* read LAM as Q 
	tst	@#accdh			;* test LAM
	bmi	L2			;* Q1=1 (conversion end)
	sob	r4,L1			;* wait untill Q=1
	br	qstil0
L2:
        .endm

	; BREAD
	;
	; This is a macro for address scan block read operation 
	; (Sub address automatic increment)
	;
	; nn	= station number
	; aa	= sub address for check the Q responce
	; word  = number of the words to be read
	; tag   = Tag code to added the read data
	;
	; register distroyed (r0,r1,r2,r4)
	;
	.macro	bread,nn,aa,word,tag
	mov	#<accbs+<nn*n>+<aa*a>>,r4  	;* set first data
	mov	#tag,r0 		 	;* TAG
	.rept	word				;* repeat 
	mov	(r4)+,r1  			;* read data
	bis	r0,r1				;* set module id bit	
	mov	r1,(r2)+			;* write data on buffer		
        .endm
        .endm

	; F0
	;=
	; This is a macro for set F=0
	;
	; register distroyed (none)
	;
	.macro	f0
	clr	@#accfn			;* set F=0
        .endm

	; F
	;
	; This is a macro for set F
	;
	; ff	= function code for check the Q responce
	;
	; register distroyed (none)
	;
	.macro	f,ff
	mov	#ff,@#accfn		;* set F
        .endm

	; NAF
	;
	; This is a macro for exeute single camac control operation
	;
	; nn	= station number of the module
	; aa	= sub address for check the Q responce
	; ff	= function code for check the Q responce
	;
	; register distroyed (none)
	;
	.macro	naf,nn,aa,ff
	mov	#ff,@#accfn			;* set F
	tst	@#<accbs+<nn*n>+<aa*a>> 	;* Exec CAMAC func.
	.endm

	; NAR
	;
	; This is a macro for exeute single camac read operation
	;
	; nn	= station number of the module
	; aa	= sub address 
	; dd    = read data
	;
	; register distroyed (none)
	;
	.macro	nar,nn,aa,dd
	mov	@#<accbs+<nn*n>+<aa*a>>,dd 	;* Exec CAMAC func.
	.endm

	; NAW
	;
	; This is a macro for exeute single camac write operation
	;
	; nn	= station number of the module
	; aa	= sub address 
	; dd    = read data
	;
	; register distroyed (none)
	;
	.macro	naw,nn,aa,dd
	mov	dd,@#<accbs+<nn*n>+<aa*a>> 	;* Exec CAMAC func.
	.endm

;
;  Comunication area between ACC and Micro VAX II computer
; 

COM::
IDR:	.word	0		; VAX -> 2180 Instruction define reg.
RSR:	.word	0		; 2180 ACC command response
STR:	.word	0		; 2180 ACC status register
VIR:	.word	0		; 2180 -> VAX Instruction define reg.
VRR:	.word	0		; VAX command response
VSR:	.word	0		; VAX status register
BPT:	.word	BPTP		; Address of buffer prologu table
MPT:	.word	MPTP		; ADDRESS of MEsessage progogu table~
BPTSAV: .word	BPTP		; Address of PBT save area for error recover	
;
;  Initialize all the system
;
init::	mov	#1000,sp	; set stack pointer #1000(o)
	SPL	0		; Set processor priority = 0
 	call	clrb1		; clear buffer 1
	call	clrb2		; clear buffer 2	
	call	setb1		; set buffer 1 write mode
	call	setvec		; set interupt vector and priority
	bic	#bufful,str	; clear buffer full sign
	mov	#iebswi,@#accim ; enable interupt from Host cpu
9$:	call	cpystr		; copy cuurent status reg. to LED	
10$:	br	10$		;

;
;  Set Interupt service routine vector
;
setvec:	mov	#isrev1,@#VECIN1  ; Extenal interupt 1 address
	mov	#prio5,@#VECIN1+2 ;                    psw
	mov	#isrev2,@#VECIN2  ; Extenal interupt 2 address
	mov	#prio5,@#VECIN2+2 ;                    psw
	mov	#isrswi,@#VECswi  ; Software interupt from host address
	mov	#prio5,@#VECswi+2 ;                             psw
	mov	#caddr,r0	  ; crate address
	mov     #<nextcr*10000>!<caddr*20000>,r0	; block header
	mov	r0,head2	;
	mov	r0,buff1+2	; Buffer 1 haeder
	mov	r0,buff2+2	; Buffer 2 haeder
	return	
;
;  Interrupt service routine from the Host processor
;
isrswi::bis	#icbswi,@#accim	; clear interupt
	bic	#iebswi,@#accim	; disable same interupt
	mov	r0,-(sp)	; save r0
	mov	r1,-(sp)	; save r1
	mov	r2,-(sp)	; save r2
	bit	#177740,idr	; check instruction pahse 1
	bne	16$		; invarid command
	bit	#37,idr		; check instruction phase 2
	beq	16$		; invarid command
	;
	; analize command and call exeute routine
	;
	bit	#1,idr		;						
	beq	1$		;
	call	clear		; clear data
1$:	bit	#2,idr		;
	beq	2$		;
	call	chgbuf		; change buffer
2$:	bit	#4,idr		;
	beq	3$		;
	call	starta		; start data acquisition
3$:	bit	#10,idr		;
	beq	4$		;
	call	stopa		; stop  data acquisition
4$:	bit	#20,idr		;
	beq	5$		;
	call	enddma		; abort DMA
5$:	br	17$		;
	;
	;  set command response (done or error) and then return
	;
16$:	mov	#100000,rsr	; set error bit of command response
	bis	#200,str	; set command error bit of status reg.
	bic	#1,str		; remove command done bit 
	br	20$		;
17$:	mov	#1,rsr		; set done succesfull bit
	bis	#1,str		; set command done bit of status reg
	bic	#200,str	; remove command error bit of str.
20$:	mov	(sp)+,r2	; restore r2
	mov	(sp)+,r1	; restore r1
	mov	(sp)+,r0	; restore r0
	bis	#iebswi,@#accim	; enable same interupt
	call	cpystr		; copy status regisoer to LED
 	rti
	;
	; Exeute each command
	;
clear: 	call	clrb1		; clear buffer 1
	call	clrb2		; clear buffer 2	
	call	setb1		; set buffer 1 write mode
	clr	evcnt		; clear event counter
	clr	bcbf		; empty 87/10/29
	bic	#340,str	; clear error bits  87/10/31
	bic	#bufful,str	; clear buffer full sign
	tst	@#<accbs+<N*nc>> ; Data way clear   88/02/29
	return
	;
chgbuf:	call	exchbf		; exchange buffer
	return
	;
starta:	bis	#2,str			; set start bit
	bis	#iebin1!iebin2,@#accim ; enable event 1,2 interupt
	bis	#iebin1!iebin2,str     ; enable event 1,2 interupt
	;NAF	NADC6,0,26.		; set 26 & read LAM as Q (2249)
	NAF	NODC1,12.,26.		; set 26 & read LAM as Q (AD811)
	NAF	NTDC1,0,26.		; set 26 & read LAM as Q (TDC)
	mov	#1.,sca			; scaler counter
	return
	;
stopa:	bic	#2,str			; clear start bit
	bic	#iebin1!iebin2,@#accim ; disable event 1,2 interupt
	bic	#iebin1!iebin2,str     ; disable event 1,2 interupt
	return
	;
enddma:	bic	#4,str		; clear dma flag
	return
;
;     Interrupt service routine from the external event 1
;  This ISR will be called event by event 
;
isrev1::bis	#icbin1,@#accim	; clear interupt
	bic	#iebin1!iebin2,@#accim	; disable same interupt
	mov	r0,-(sp)	; save r0
	mov	r1,-(sp)	; save r1
	mov	r2,-(sp)	; save r2
	mov	r3,-(sp)	; save r3
	mov	r4,-(sp)	; save r4
				;
	mov	bcbw,r3		; address of Buffer Control Block 
	mov	12(r3),r2	; current buffer pointer --> r2
	mov	2(r3),r1	; buffer absolute limit ---> r1
	cmp	r1,r2		; enough room for next data ?
	bhi	3$		;   yes. these is some room
	jmp	nextev		;   no, buffer is now in the end point
3$:	mov	#maxevl,r0	; Max event length
	asl	r0		; *2 (two event)
	sub	r0,r1		; possible maxmum next event length
	cmp	r1,r2		; should I requeste to change the buffer ?
	bhi	5$		;   no, enough room for nexe event
	bis	#bufful,str	;   yes, then assert buffer full sign
5$:	inc	evcnt		; increment event counter
	;
	; Write Event Header
	;
	mov	evcnt,r0	; Event counter --> r0
	bic	#177400,r0	; Clear high 8-bit
	bis	#head,r0	; Write header (EE(Hex)) in high 8 bits
	mov	r2,pstart	; Save pointer
	mov	r0,(r2)+	;
	mov	r2,pleng	; Save pointer
	tst	(r2)+		; Data length area
	;
;---------------- From here, you can modify --------------------
	;
	;  Read common parameter  RDI=0
	;
	;
	;  RID=1 data (30 bytes)
	;
	mov	#<1*400+30.>,(r2)+	; RID=1
	;
        ;
	; Read 4208 Real time TDC 2chs
	;
	F	0
	NAR	nrtdc,0,(r2)+	; R TDC-0
	NAR	nrtdc,1,(r2)+	; R TDC-1
	;
	; Wait Conversion end of ADC/TDC
	;
	;
;	WAITQ	nadc1,0.,8.,30.,50$	; Lecroy 2249w (LAM wait)
	WAITQ	nodc1,12.,8.,30.,50$	; Ortec 811 (LAM wait)
	F	2			; read and clear
50$:	NAR	nodc1,0,(r2)+	; ADC-0
	NAR	nodc1,1,(r2)+	; ADC-1
	NAR	nodc1,2,(r2)+	; ADC-2
	NAR	nodc1,3,(r2)+	; ADC-3
	NAR	nodc1,4,(r2)+	; ADC-4
	NAR	nodc1,5,(r2)+	; ADC-5
	;
	WAITQ	nqdc1,0.,8.,30.,51$	; QDC
51$:	F0
	NAR	nqdc1,0,(r2)+	; QDC-1  Plastic 1 L
	NAR	nqdc1,1,(r2)+	; QDC-1  Plastic 2 H
	;
	F	0
52$:	NAR	ntdc1,0,(r2)+	; TDC
	NAR	ntdc1,1,(r2)+	; TDC
	;	
        NAR     nqdc1,2,(r2)+   ; QDC-1    Plastic 2 L
        NAR     nqdc1,3,(r2)+   ; QDC-1    Plastic 2 H
	
nextev:				; Do not delete this line
	;
	; Clear module
	;
	naf	nodc1,7,2.	; clear ORTEC ADC
	naf	nqdc1,0,9.	; clear Lecroy QDC 1
	naf	ntdc1,0,9.	; clear Lecroy TDC 1
	naf	nrtdc,0,9.	; clear Lecroy RTDC 
;--------- Never change bellow-------------------------------------
	;
	mov	r2,12(r3)	; r2 = resore current buffer pointer 
	sub	pstart,r2	; Buffer length of this event 
	mov	pleng,r1	; Restore pointer
	mov	r2,(r1)		; Write length of this event
35$:	mov	(sp)+,r4	; restore r4
	mov	(sp)+,r3	; restore r3
	mov	(sp)+,r2	; restore r2
	mov	(sp)+,r1	; restore r1
	;
	; Output pulse to Output register bit 9 / (0-15)
	;
	mov	str,r0		; ACC status register
	mov	#16.,@#accfn	; set F=16
	bis	#endisr,r0
	mov	r0,@#<accbs+<N*Nopr>> ; Copy STR to output reg o9=1
	tst	str		; wait a little	
	bic	#endisr,r0
	mov	r0,@#<accbs+<N*Nopr>> ; Copy STR to output reg o9=0
	mov	(sp)+,r0	; restore r0
	;
	; Reenable next event and Rerutn form the interupt
	;
	bis	#iebin1!iebin2,@#accim	; enable same interupt
 	rti

;
;     Interrupt service routine from the external event 2
;  This ISR will be called when the buffer is filled in multi-crate mode
;
isrev2::bis	#icbin2,@#accim		; clear interupt
	mov	@#accim,-(sp)   	; save interupt mask
	mov	r0,-(sp)		; save r0
	bic	#iebin2!iebin1,@#accim	; disable interupt 1 and 2
	bis	#bufful,str		; assert buffer full sign
	mov	#16.,@#accfn		; set F=16
	mov	r0,@#<accbs+<N*Nopr>> 	; Copy STR to output reg (set busy)
	mov	r1,-(sp)		; save r1
	mov	r2,-(sp)		; save r2

        call	exchbf			; Exchange buffer

	mov	(sp)+,r2		; restore r2
	mov	(sp)+,r1		; restore r1
	mov	(sp)+,r0		; restore r0
	bis	#iebin2,str		; enable same interupt
	bic	#bufful,str		; clear buffer full sign
	mov	#16.,@#accfn		; set F=16
	mov	str,@#<accbs+<N*Nopr>> 	; Copy STR to output reg (clear busy)
	mov	(sp)+,@#accim   	; save interupt mask
 	rti
;
; Exchange buffer
;
;    Resister ddstroyed :   r0, r1, r2
;
EXCHBF:	tst	bcbf		; Is there any empty buffer ?
;	beq	1$		; yes	
	br	1$
		
	mov	bptsav,bpt	; restore bpt address 87/10/29
	call	waitbf		; waiting for buffer
	bcs	11$		; Error detected 87/10/30
1$:	mov	bcbw,r0		; current write
	bne	2$		;
	call	errbuf		; error
	;
	; no error detected
	;
2$:	mov	r0,bcbf		; 
	mov	(r0),r2		; buffer header address --> R2
	mov	12(r0),r1	; buffer end address    --> R1
	sub	(r0),r1		; buffer length         
	add	#10,r1		; add header length
	mov	r1,6(r2)	; write buffer header (length)
	mov	evcnt,r1	; event couner
	clr     evcnt		; clear event count
	bic     #170000,r1	; clear high 4 bit
	mov	head2,2(r2)	; write header (Crate address, flag)
	bis	r1,2(r2)	; write header (event count)
	cmp	#1,bcbw+2	; buff 1 ?
	bne	5$		;
	;
	; previous buffer is no. 1
	;
	mov	#2,vir		; set buff 1 full flag
	mov	bcb1,bcbf	; set data full pointer
	call	setb2		; set buffer 2 for next data acpu.
	br	10$		;
	;
	; previous buffer is no. 2
	;
5$:	mov	#4,vir		; set buff 2 full flag
	mov	bcb2,bcbf	; set data full pointer
	call	setb1		; set buffer 1 for next data acq
	;
	; Tell to the host cpu that the buffer is full
	; through the LAM
	;
10$:	call	cpystr		; status register
        tst	#caddr		; test acc address
	bne	11$		; only master crate genarates LAM
	bis	#4,str		; set dma flag 
	bis	#icblam,@#accim	; Genarate LAM
11$:    return
	;
	; There is now no room for next buffer
	; waiting for buffer room
	;
waitbf::mov	r0,-(sp)	;
	mov	r1,-(sp)	;
	mov	#100.,r1	; wait 5*100= 500 mill sec.
1$:	mov	#1000.,r0 
2$:	sob	r0,2$		; wait 5 mill sec.
	tst	bcbf
	beq	10$		; buffer is ready
	sob	r1,1$		; repeat until timeout
	call	errbuf		; error detected in buffer
	sec			; set carry (error)
	br	11$		; 
10$:	clc			; no error
11$:	mov	(sp)+,r1	;
	mov	(sp)+,r0	;
	return
	;
	; Fatal error in buffer manipuration
	; Notify to host and Recover buffer status 
	;
errbuf:	bis	#100,str	; set buffer error bit
	call	cpystr		; status register
	mov	bptsav,bpt	; restore bpt address 87/10/29
	mov	bcb1s,bcb1	; resotre 87/10/30
	mov	bcb2s,bcb2	; resotre 87/10/30
	call	clrb1		; clear buffer 1
	call	setb1		; set buffer 1
	clr	bcbf		; set empty 
	mov	#400,vir	; set buffer error flag
;	bis	#icblam,@#accim	; Genarate LAM
	return			; stop cpu


;
;  Copy status register to camac LED
;
CPYSTR:	mov	r0,-(sp)	 ; Save r0
	mov	@#accfn,-(sp) 	 ; Save current function reg.
	mov	@#accdh,-(sp) 	 ; Save current function reg.
	mov	#16.,@#accfn	 ; F16
	clr	@#accdh		 ; data high
	tst	str		 ; wait a little
	mov	@#accim,r0	 ; interupt mask register
	clrb	r0		 ; clear lower 8 bit
	bic     #100000,r0	 ; clear MSB of r0
	bic	#077400,str	 ; clear high byte (except for bit 16)
	add	r0,str		 ; add status register
	mov	(sp)+,@#accdh	 ; retrore previous function reg.
	mov	(sp)+,@#accfn	 ; retrore previous function reg.
	mov	(sp)+,r0	 ; resoter r0
	return			 ; return


;
;  Clear buffer 1 or 2
;
CLRB1:	mov	bcb1,r0		; address of buffer controll block 1
	br	clrb		;
CLRB2:	mov	bcb2,r0		; address of buffer controll block 2
				;
CLRB:	mov	(r0),r1		; address of the buffer
	mov	4(r0),r2	; length of the buffer in byte
        add	#6,r1		; do not delete buffer header
	sub     #6,r2		;    "
	asr	r2		; 		       in word
1$:	clr	(r1)+		; clear buffer region
	sob	r2,1$		; loop
				;
	clr	6(r0)		; clear buffer status register
	mov	(r0),12(r0)	; copy top address to write pointer
	mov	(r0),14(r0)	; copy top address to read pointer
	return
;
;  Set buffer 1 or 2 
;
setb1:	mov	r0,-(sp)	;
	mov	bcb1,r0		; address of buffer controll block 1
	mov	#1,bcbw+2	; buffer number for write
	bis	#10,str		; buff 1 in use
	bic	#20,str		; buff 2 not in use
	mov	head2,buff1+2	; Clear header
	br	setb		;
setb2:	mov	r0,-(sp)	;
	mov	bcb2,r0		; address of buffer controll block 2
	mov	#2,bcbw+2	; buffer number for write
	bic	#10,str		; buff 1 not in use
	bis	#20,str		; buff 2  in use
	mov	head2,buff2+2	; Clear header
				;
setb:	mov	r0,bcbw		; BPT for write
	mov	(r0),r1		; address of the buffer
        add	#10,r1		; header area 90/04.26
	mov	r1,12(r0)	; copy top address to write pointer
	mov	#2,6(r0)	; status <= Write mode
	mov	(sp)+,r0	;
	return
				;
;
; Buffer prologu table
;
BPTP::
BCBW:	.word	0		; Address of BCB for current write
	.word	0		; Buffer no. for current write
BCBR:	.word	0		; Address of BCB for current read
	.word	0		; Buffer no. for current read
BCBF:	.word	0		; Address of BCB for data full
	.word	0		; Buffer no. for data full
	.word   0,0		; reserved
BCB1:	.word	BCBA1		; Address of Buffer control Block 1
BCB2:	.word	BCBA2		; Address of Buffer control Block 2
	.word	0,0,0,0,0,0	; (Reserved)
;
; For error recover
;
BCB1S:	.word	BCBA1		; Address of Buffer control Block 1
BCB2S:	.word	BCBA2		; Address of Buffer control Block 2
;
; Buffer control block 1
;
BCBA1:	.word	BUFF1		; Address of the buffer
	.word	BUFF1+BUFL	; Limit of the buffer
	.word	BUFL		; Length of the buffer in byte
	.word	0		; Status of buffer
	.word	0		; Access Inter-loock
	.word	BUFF1		; Write data pointer
	.word	BUFF1		; Read data pointer
	.word	0		; (Reserved)
;
; Buffer control block 2
;
BCBA2:	.word	BUFF2		; Address of the buffer
	.word	BUFF2+BUFL	; Limit of the buffer
	.word	BUFL		; Length of the buffer in byte
	.word	0		; Status of buffer
	.word	0		; Access Inter-loock
	.word	BUFF2		; Write data pointer
	.word	BUFF2		; Read data pointer
	.word	0		; (Reserved)
;
;  Buffer Data area
;
evcnt:: .word   0		; event conter
head2::	.word	0		; Hedder backup
pleng::	.word	0		; 
pstart::.word	0		; Buffer start temporary pointer
sca::   .word	0
	.even
BUFF1::	.word   0		;2-byte zero
	.word	0		; Caddr/Netctr/Event counter
	.word	BUFL		;block size of this buffer.
	.word   0		;effective data length
	.blkb	BUFL		;buffer 1 region
BUFF2::	.word	0		;buffer 2 region
	.word	0		; Caddr/Netctr/Event counter
	.word	BUFL		;block size of this buffer.
	.word   0		;effective data length
	.blkb	BUFL		;buffer 1 region
;
; Massage prologu table
;
MPTP::
exit:	halt			;return to moniter	
	.end	init